Electronic Component Survivability in Harsh Environments
Dr. Pradeep Lall
Aerospace and missile applications require electronics to sustain high-acceleration levels during normal operation. Missile applications increasingly use commercial-off the shelf electronics components with the expectation of reliable operation under acceleration loads upto 50,000g. Unlike consumer electronics, military systems have longer lifetimes in the neighborhood of 20-40 years and higher reliability requirements. Reduced size and geometry constraints imposed on electronics in various harsh environment applications has motivated a tremendous demand for use of very fine pitch surface mount electronics. Fine pitch BGAs of 0.4mm and 0.5mm pitch are finding applications in military and defense applications. Commercial-off-the-Shelf (COTS) parts are increasingly being used for military and defense applications. Survivability of electronics in consumer applications is often ascertained using the JEDEC Test Standard JESD22-B111. The test standard prescribes the application of a 1500g, 0.5ms shock pulse to the board assembly. Survivability and design envelope of fine pitch semiconductor packages under high-g mechanical shock in the range of 10,000g-50,000g of mechanical shock is unknown. In addition, the efficacy of the traditional supplemental restraint mechanisms such as underfills in mitigating the risk of interconnect failure under high-g mechanical shock, is not available.
Electronics in missile fuzing applications may be subjected to high-g mechanical shock during storage and transport prior to deployment. In this study, methods will be developed to mitigate the effect of mechanical on fine-pitch electronics. Shock loads upto 30,000g of acceleration will be studied on area-array electronic components. Supplemental restraint mechanisms studied will include use of underfills, and potting compounds. Correlation between the material properties of underfills and potting compounds and their end use performance will be developed. Metrics will be identified for the assessment of expected end use performance of supplemental restraint mechanisms. Assemblies developed for use in the study will include both leadfree solders and compliant interconnects. The compliant interconnect formats targeted will include – polymer balls on area-array BGAs subjected to high-g mechanical shock. Explicit finite element models will be developed to develop a predictive methodology for assessment of the transient dynamic behavior of board assemblies in both potted and unreinforced configuration.